Pipelining - Revision history

Demindiro: Fix example clockrate

2025-03-19T19:39:43Z

Fix example clockrate

← Older revision		Revision as of 19:39, 19 March 2025
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	Hence, reducing the delay before a signal can hit a storage cell allows increasing clock speed.		Hence, reducing the delay before a signal can hit a storage cell allows increasing clock speed.

	For example, take the time profile a naive CPU design which executes a single instruction per cycle, at 0.~~5MHz~~:		For example, take the time profile a naive CPU design which executes a single instruction per cycle, at 0.33MHz:
	<source>		<source>
	0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs		0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs
Line 9:		Line 9:
	xor x1,x3 \|--------------------\|		xor x1,x3 \|--------------------\|
	</source>		</source>
	By splitting instruction fetch, decode, and execute into separate stages we might be able to increase the clock rate to 1.~~5MHz~~:		By splitting instruction fetch, decode, and execute into separate stages we might be able to increase the clock rate to 1.00MHz:
	<source>		<source>
	0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs		0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs

Demindiro: Draft

2025-03-18T20:30:09Z

Draft

New page

A limiting factor in CPU performance is transistor '''propagation delay''': the amount of time it takes for a signal to traverse from start to end.
Hence, reducing the delay before a signal can hit a storage cell allows increasing clock speed.

For example, take the time profile a naive CPU design which executes a single instruction per cycle, at 0.5MHz:
<source>
0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs
add x1,x5 |--------------------|
ror x2,x4 |--------------------|
xor x1,x3 |--------------------|
</source>
By splitting instruction fetch, decode, and execute into separate stages we might be able to increase the clock rate to 1.5MHz:
<source>
0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs
add x1,x5 |--IF--|--ID--|--EX--|
ror x2,x4 |--IF--|--ID--|--EX--|
xor x1,x3 |--IF--|--ID--|--EX--|
</source>
Note that the fetch, decode and execute stages are independent. We can overlap these stages...:
<source>
0µs 1µs 2µs 3µs 4µs 5µs 6µs 7µs 8µs 9µs
add x1,x5 |--IF--|--ID--|--EX--|
ror x2,x4 |--IF--|--ID--|--EX--|
xor x1,x3 |--IF--|--ID--|--EX--|
</source>
... reducing total execution time from 9µs to 5µs!