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	<id>https://cpudev.org/w/index.php?action=history&amp;feed=atom&amp;title=Instruction_encoding</id>
	<title>Instruction encoding - Revision history</title>
	<link rel="self" type="application/atom+xml" href="https://cpudev.org/w/index.php?action=history&amp;feed=atom&amp;title=Instruction_encoding"/>
	<link rel="alternate" type="text/html" href="https://cpudev.org/w/index.php?title=Instruction_encoding&amp;action=history"/>
	<updated>2026-04-25T16:31:05Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
	<generator>MediaWiki 1.36.1</generator>
	<entry>
		<id>https://cpudev.org/w/index.php?title=Instruction_encoding&amp;diff=26&amp;oldid=prev</id>
		<title>Demindiro: Hardwired zero register</title>
		<link rel="alternate" type="text/html" href="https://cpudev.org/w/index.php?title=Instruction_encoding&amp;diff=26&amp;oldid=prev"/>
		<updated>2025-03-19T20:34:00Z</updated>

		<summary type="html">&lt;p&gt;Hardwired zero register&lt;/p&gt;
&lt;table style=&quot;background-color: #fff; color: #202122;&quot; data-mw=&quot;interface&quot;&gt;
				&lt;col class=&quot;diff-marker&quot; /&gt;
				&lt;col class=&quot;diff-content&quot; /&gt;
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				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Revision as of 20:34, 19 March 2025&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot; id=&quot;mw-diff-left-l30&quot;&gt;Line 30:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Line 30:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;24-bit  xxxxxxxx  xxxxxxxx  xxxxx011&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;24-bit  xxxxxxxx  xxxxxxxx  xxxxx011&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&amp;lt;/source&amp;gt;&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&amp;lt;/source&amp;gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;=== Hardwired zero register ===&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;A substantial amount of instructions can be omitted by having a register which always reads 0.&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br/&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br/&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;=== Implicit destination registers ===&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;=== Implicit destination registers ===&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>Demindiro</name></author>
	</entry>
	<entry>
		<id>https://cpudev.org/w/index.php?title=Instruction_encoding&amp;diff=21&amp;oldid=prev</id>
		<title>Demindiro: Draft</title>
		<link rel="alternate" type="text/html" href="https://cpudev.org/w/index.php?title=Instruction_encoding&amp;diff=21&amp;oldid=prev"/>
		<updated>2025-03-18T19:59:37Z</updated>

		<summary type="html">&lt;p&gt;Draft&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;There are many different ways to encode instructions, all with their own tradeoffs.&lt;br /&gt;
&lt;br /&gt;
== Considerations ==&lt;br /&gt;
&lt;br /&gt;
=== Fixed-width or variable-length ===&lt;br /&gt;
&lt;br /&gt;
Even among variable-length ISAs there is a broad spectrum in complexity. For example, x86 is notorious for being difficult to decode. In contrast, RISC-V is also variable-length but trivial to decode.&lt;br /&gt;
&lt;br /&gt;
=== Instruction density ===&lt;br /&gt;
&lt;br /&gt;
Large instructions can encode many things but have poor density, while smaller instructions have good density but may not be able to encode many things.&lt;br /&gt;
&lt;br /&gt;
Of particular note is the amount of directly addressable registers: a larger amount of registers requires more bits to encode, leaving less to encode other things.&lt;br /&gt;
&lt;br /&gt;
=== Instruction formats ===&lt;br /&gt;
&lt;br /&gt;
To reduce decoding complexity it is wise to define a few fixed formats, which all instructions should be defined in terms of.&lt;br /&gt;
&lt;br /&gt;
== Techniques ==&lt;br /&gt;
&lt;br /&gt;
=== Variable-length encoding ===&lt;br /&gt;
&lt;br /&gt;
To keep decoding variable-length instructions simple one can use a fixed prefix of a few bits.&lt;br /&gt;
&lt;br /&gt;
For example, an ISA with 8, 16 and 24-bit instructions could be encoded as:&lt;br /&gt;
&amp;lt;source&amp;gt;&lt;br /&gt;
        23    16  15     8  7      0&lt;br /&gt;
 8-bit                      xxxxxxx0&lt;br /&gt;
16-bit            xxxxxxxx  xxxxxx01&lt;br /&gt;
24-bit  xxxxxxxx  xxxxxxxx  xxxxx011&lt;br /&gt;
&amp;lt;/source&amp;gt;&lt;br /&gt;
&lt;br /&gt;
=== Implicit destination registers ===&lt;br /&gt;
&lt;br /&gt;
Instead of having explicitly named registers, one can instead have a queue of registers and address source registers relative to the &amp;quot;instruction distance&amp;quot;.&lt;br /&gt;
&lt;br /&gt;
Aside from being useful for out-of-order processors, this also avoids the need to encode a destination, freeing bits for other purposes.&lt;/div&gt;</summary>
		<author><name>Demindiro</name></author>
	</entry>
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